U.S. Government Accelerates Post-Quantum Cryptography Migration Across Federal and Defense Systems

The United States has entered a new phase in the transition to post-quantum cryptography. The White House OMB Memorandum M-26-15, Execution of the Migration to Post-Quantum Cryptography, together with the Executive Order “Securing the Nation Against Advanced Cryptographic Attacks“ and the Department of War’s Post-Quantum Cryptography Strategy, establishes PQC migration […]

PQSecure™-Agility Earns NIST CAVP Validation

We are thrilled to announce that PQSecure™-Agility, our comprehensive hardware/software co-design framework for crypto-agile security, has officially achieved NIST CAVP validation. As the global transition to quantum-safe cryptography accelerates, the industry faces a dual challenge: implementing next-generation algorithms while simultaneously defending against sophisticated physical threats. PQSecure™-Agility solves this by delivering […]

PQSecure Welcomes Cryptography Veteran Mike Borza to Accelerate Quantum-Safe Growth

We’re excited to welcome Mike Borza to the team at PQSecure! Mike Borza is a seasoned cryptography veteran with decades of experience spanning product security, silicon IP, EDA ecosystems, and advanced cryptographic technologies—including post-quantum cryptography. His background in shaping secure products and working closely with industry leaders brings tremendous strategic […]

Securing the Future With Post-Quantum Cryptography on Microchip FPGAs

? Post-Quantum Cryptography must be real, deployable, and secure — across software and silicon. This recent Microchip Technology Inc. blog on Post-Quantum Cryptography on FPGAs highlights an important industry shift: hashtag#PQC is moving beyond theory and into hardware platforms that actually ship.? https://lnkd.in/eQXW5Tw6 At PQSecure, this direction strongly resonates with our […]

PQSecure Collaborates with George Mason University on NIST Lightweight Cryptography Hardware Research

PQSecure Technologies collaborated with George Mason University (GMU) on a landmark peer-reviewed research publication titled “Lightweight Champions of the World: Side-Channel Resistant Open Hardware for Finalists in the NIST Lightweight Cryptography Standardization Process,” published in ACM Transactions on Embedded Computing Systems. This work represents the first coordinated, large-scale effort to design, implement, and evaluate side-channel-resistant open hardware for finalists […]

PQSecure CEO Featured on Embedded Executive Podcast

PQSecure’s Founder and CEO, Reza Azarderakhsh, was recently featured on the Embedded Executive podcast, where he discussed the growing importance of post-quantum cryptography (PQC) and secure silicon design in the context of the CHIPS and Science Act. In the episode, Reza shares insights on why quantum-safe cryptography, hardware/software co-design, and trusted cryptographic IP are becoming critical […]

PQSecure Achieves NIST CAVP Validation

We’re proud to announce that PQSecure’s Rust cryptographic libraries have been officially validated through NIST’s Cryptographic Algorithm Validation Program (CAVP). This validation covers a comprehensive suite of post-quantum and classical algorithms, including: These libraries are designed to meet the high-assurance demands of embedded systems and other mission-critical applications—advancing trusted, quantum-safe […]

From Theory to the Field: Why Side-Channel Protection Defines Post-Quantum Security

A new article by our PQSecure team is now live on Design & Reuse, in which a critical and often overlooked aspect of PQC, side-channel protection, is discussed. While post-quantum algorithms may be mathematically secure, real-world deployments require resistance to physical attacks. In this article, we explain why side-channel countermeasures […]

Enabling Crypto Agility Through HW/SW Co-Design with Menta

In collaboration with Menta, PQSecure has demonstrated how hardware/software co-design with eFPGA can deliver both performance and flexibility for post-quantum cryptography. By partitioning the XMSS algorithm, our approach lets processor manage dataflow and memory, while the eFPGA accelerates computationally heavy lattice-based operations. The result: This design flow, which is supported […]

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