Intellectual property
PQSecure Patent Portfolio
This portfolio includes issued U.S. patents and pending U.S. and international patent applications. Filing years shown.
Issued U.S. Patents
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Computer Processing System and Method Configured to Perform Side-Channel Countermeasures
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Computer Processing System and Method for Lower-Order Masking in Higher-Order Masked Designs
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Cryptographic Processing System for CRYSTALS-Kyber and CRYSTALS-Dilithium Using Masked A2B Conversion
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Hardware Architecture Implementing ASCON Cryptographic Algorithms with Side-Channel Protection
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Computer Architecture and Method for Performing Lattice-Based Cryptographic Primitives with Resistance to Side-Channel Attacks
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A Fast Multi-Core Method and System for Chaining Isogeny Computations
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A Low-Footprint Resource-Sharing Hardware Architecture for CRYSTALS-Dilithium and CRYSTALS-Kyber
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A Method and System for Computing Large-Degree Isogenies with an Odd Degree
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An Area-Efficient Architecture for Lattice-Based Key Encapsulation and Digital Signature Generation
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Computer Processing Architecture and Method for Supporting Multiple Public-Key Cryptosystems Based on Exponentiation
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A Low-Footprint Hardware Architecture for Kyber-KEM
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An Architecture for Small and Efficient Modular Multiplication Using Carry-Save Adders
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Architecture and Method for Hybrid Isogeny-Based Cryptosystems
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Efficient Hardware Architecture for Highly Secure Isogeny-Based Cryptosystems
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High-Performance Systems to Validate Isogeny-Based Cryptography Keys
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Randomization Methods in Isogeny-Based Cryptosystems
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Cryptosystem and Method Using Isogeny-Based Computations to Reduce a Memory Footprint
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Efficient Architecture and Method for Arithmetic Computations in Post-Quantum Cryptography
Pending Patent Applications
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Computer-Implemented Method and System of Performing Side-Channel Protected Operations
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Lattice Coprocessor Architecture for Lattice-Based Cryptography
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Scalable Hardware Architecture Configured to Perform a Hash-Based Signature Algorithm
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Hardware Configuration for Executing ASCON Cryptographic Methods with Side-Channel Defense
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Low-Footprint, Memory-Efficient Hardware Architecture Supporting Multiple Cryptographic Modules
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Circuit Hardware Architecture Configured to Generate Randomness
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Computer-Implemented Method for Computing Unbalanced L-Trees for Hash-Based Signatures in Post-Quantum Authentication
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Hardware- or Software-Based Method for Enhancing Resistance Against Side-Channel Attacks
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Method for Implementing Left-Node Authentication in XMSS and LMS Hash-Based Signatures
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Low-Footprint Hardware Architecture for Dilithium Digital Signature Scheme
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Low-Overhead Method and Architecture for Side-Channel Attack Resistance in Elliptic Curve Arithmetic
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Method and Architecture for Computing Extension Field Arithmetic in a Cryptosystem
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A Computer Chip and Method of Utilizing a Lattice Coprocessor with a Computer Processor to Perform Computations for a Lattice-Based Cryptography Algorithm
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