PQSecure Patent Portfolio
This portfolio includes issued U.S. patents and pending U.S. and international patent applications. Filing years shown.
Issued U.S. Patents
Computer Processing System and Method Configured to Perform Side-Channel Countermeasures
Computer Processing System and Method for Lower-Order Masking in Higher-Order Masked Designs
Cryptographic Processing System for CRYSTALS-Kyber and CRYSTALS-Dilithium Using Masked A2B Conversion
Hardware Architecture Implementing ASCON Cryptographic Algorithms with Side-Channel Protection
Computer Architecture and Method for Performing Lattice-Based Cryptographic Primitives with Resistance to Side-Channel Attacks
An Area-Efficient Architecture for Lattice-Based Key Encapsulation and Digital Signature Generation
A Fast Multi-Core Method and System for Chaining Isogeny Computations
A Method and System for Computing Large-Degree Isogenies with an Odd Degree
Computer Processing Architecture and Method for Supporting Multiple Public-Key Cryptosystems Based on Exponentiation
A Low-Footprint Resource-Sharing Hardware Architecture for CRYSTALS-Dilithium and CRYSTALS-Kyber
High-Performance Systems to Validate Isogeny-Based Cryptography Keys
A Low-Footprint Hardware Architecture for Kyber-KEM
Randomization Methods in Isogeny-Based Cryptosystems
An Architecture for Small and Efficient Modular Multiplication Using Carry-Save Adders
Architecture and Method for Hybrid Isogeny-Based Cryptosystems
Efficient Hardware Architecture for Highly Secure Isogeny-Based Cryptosystems
Cryptosystem and Method Using Isogeny-Based Computations to Reduce a Memory Footprint
Efficient Architecture and Method for Arithmetic Computations in Post-Quantum Cryptography
Pending Patent Applications
A Computer Chip and Method of Utilizing a Lattice Coprocessor with a Computer Processor to Perform Computations for a Lattice-Based Cryptography Algorithm
Computer-Implemented Method and System of Performing Side-Channel Protected Operations
Lattice Coprocessor Architecture for Lattice-Based Cryptography
Scalable Hardware Architecture Configured to Perform a Hash-Based Signature Algorithm
Hardware Configuration for Executing ASCON Cryptographic Methods with Side-Channel Defense
Low-Footprint, Memory-Efficient Hardware Architecture Supporting Multiple Cryptographic Modules
Circuit Hardware Architecture Configured to Generate Randomness
Hardware- or Software-Based Method for Enhancing Resistance Against Side-Channel Attacks
Method for Implementing Left-Node Authentication in XMSS and LMS Hash-Based Signatures
Computer-Implemented Method for Computing Unbalanced L-Trees for Hash-Based Signatures in Post-Quantum Authentication
Low-Overhead Method and Architecture for Side-Channel Attack Resistance in Elliptic Curve Arithmetic
Method and Architecture for Computing Extension Field Arithmetic in a Cryptosystem
Low-Footprint Hardware Architecture for Dilithium Digital Signature Scheme